Abstract

Integrated circuit design is entering an era of truly nanoscale transistors with minimum device geometries now at 32nm and soon to be at 25nm. While actual transistor and logic gate sizes are many times the minimum lengths possible, logic elements are becoming increasingly small and more closely packed together. There is now an increasing possibility of getting coupling errors where nearby logic gates and wires can induce an erroneous response in a logic gate. This has been a significant problem in memory systems for many years where techniques to test for this fault mechanism are well developed. In logic test, there are few methodologies or technologies for detecting this new category of errors.