Abstract

In this paper a multi-platform HDL description of a circuit that implements all the digital processing and RF carrier generation for the class S Power Amplifier proposed by the Institute of Microelectronics and Wireless Systems is presented. The circuit is the combination of a lowpass sigma-delta modulation stage in series with a frequency shifting stage that generates the bitstream that drives a switch mode amplifier followed by a bandpass filter. This HDL description is that it can be implemented not only on high-end FPGAs but on low-cost devices as well. The 8 parameters that define at compilation time the final implementation are presented and four implementations are discussed in this work. The design is validated with data measured in the simulation and in the prototype.