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Modelling and Design of High-Order Phase Locked Loops

UNSPECIFIED (2005) Modelling and Design of High-Order Phase Locked Loops. In: UNSPECIFIED.

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Abstract

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The max value of gain where all the poles lie inside the unit circle is the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above Bessel filter system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Item Type: Conference or Workshop Item (Other)
Additional Information: Copyright 2004 Society of Photo-Optical Instrumentation Engineers. This paper was published in [add journal or proceedings bibliographic information] and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.
Keywords: Digital Phase Lock Loop,
Subjects: Science & Engineering > Electronic Engineering
Item ID: 575
Depositing User: Dr. Ronan Farrell
Date Deposited: 29 Jun 2007
Publisher: SPIE
URI:

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