Embedded Test Engine For Efficient At-Speed Scan Testing and Performance Binning of Microprocessors
Lawlor, Eddie and Farrell, Ronan (2004) Embedded Test Engine For Efficient At-Speed Scan Testing and Performance Binning of Microprocessors. .
In this paper a modified architecture for
at-speed scan testing is presented. This new
architecture addresses the trend in the
semiconductor industry for increased at-speed
structural testing. The proposed architecture offers
reduced time for standard at-speed testing, and, in
particular, substantial savings for the repeated atspeed
testing required for microprocessor speed and
performance binning. The architecture has been
demonstrated on UMC 0.18Î¼m and has achieved
with little die overhead.
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|Keywords:||at-speed scan testing, performance
speed binning, design-for-test, embedded test.|
|Subjects:||Science & Engineering > Electronic Engineering|
|Deposited By:||Dr. Ronan Farrell|
|Deposited On:||04 Jul 2007|
|Publisher:||IEEE: Institute of Electrical and Electronics Engineers|
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