Built-In Test Engine For Memory Test
McEvoy, Paul and Farrell, Ronan (2004) Built-In Test Engine For Memory Test. .
In this paper we will present an on-chip
method for testing high performance memory
devices, that occupies minimal area and retains full
flexibility. This is achieved through microcode test
instructions and the associated on-chip state
machine. In addition, the proposed methodology
will enable at-speed testing of memory devices. The
relevancy of this work is placed in context with an
introduction to memory testing and the techniques
and algorithms generally used today.
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|Keywords:||BIST, memory, at-speed, DFT|
|Subjects:||Science & Engineering > Electronic Engineering|
|Deposited By:||Dr. Ronan Farrell|
|Deposited On:||04 Jul 2007|
|Publisher:||IEEE: Institute of Electrical and Electronics Engineers|
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