Built-In Test Engine For Memory Test
McEvoy, Paul and Farrell, Ronan (2004) Built-In Test Engine For Memory Test. . AbstractIn this paper we will present an on-chip
method for testing high performance memory
devices, that occupies minimal area and retains full
flexibility. This is achieved through microcode test
instructions and the associated on-chip state
machine. In addition, the proposed methodology
will enable at-speed testing of memory devices. The
relevancy of this work is placed in context with an
introduction to memory testing and the techniques
and algorithms generally used today. | Additional Information: | Copyright é 2005 IEEE.  Reprinted from (relevant publication info).
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| Keywords: | BIST, memory, at-speed, DFT |
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| Subjects: | Science & Engineering > Electronic Engineering |
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| ID Code: | 589 |
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| Deposited By: | Dr. Ronan Farrell |
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| Deposited On: | 04 Jul 2007 |
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| Publisher: | IEEE: Institute of Electrical and Electronics Engineers |
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| Refereed: | Yes |
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