Duignan, Nigel and Farrell, Ronan
An Architecture for a reconfigurable charge-summation based ADC.
Presented in this paper is a low power, area efficient reconfigurable analog-to-digital (ADC) converter, utilising a charge-summation technique with a switched-capacitor implementation. Using a non-inverting switched-capacitor integrator a staircase ramp is produced using switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a reconfigurable ADC for use in a reconfigurable radio.
Conference or Workshop Item
||This paper is a postprint of a paper submitted to and accepted for publicatin in (journal/conference)
and is subject to Institution of Engineering and Technology Copyright. The copy of record is
available at IET Digital Library
||Switched-capacitor, charge-summation, linearity, reconfigurable radio.
||Science & Engineering > Electronic Engineering
Dr. Ronan Farrell
||12 Jul 2007
||Institution of Engineering and Technology
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