Design Of High Frequency Digital Phase Locked Loops
Daniels, Brian and Farrell, Ronan (2006) Design Of High Frequency Digital Phase Locked Loops. . AbstractThis paper considers the stability of high order Charge Pump
Phase Lock Loop (CP-PLL), proposing a novel means of
identifying stable regions for such systems. Traditional design
techniques are inefficient for high frequency, high order CPPLL
systems. This paper proposes an accurate and efficient
means of identifying stable regions for 2nd and 3rd order high
frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL
responses it is shown that the proposed stability technique is a
significant improvement over existing linear methods. | Additional Information: | This paper is a postprint of a paper submitted to and accepted for publicatin in (journal/conference)
and is subject to Institution of Engineering and Technology Copyright. The copy of record is
available at IET Digital Library
|
|---|
| Keywords: | Stability, Charge Pump, Phase Locked Loop, High
Frequency. |
|---|
| Subjects: | Science & Engineering > Electronic Engineering |
|---|
| ID Code: | 601 |
|---|
| Deposited By: | Dr. Ronan Farrell |
|---|
| Deposited On: | 12 Jul 2007 |
|---|
| Publisher: | Institution of Engineering and Technology |
|---|
| Refereed: | Yes |
|---|
| URL: | http://www.theiet.org/publications/ |
|---|
Repository Staff Only: item control page
|
![[img]](http://eprints.nuim.ie/style/images/fileicons/application_pdf.png)